The present invention relates to an emitter-follower circuit and, more particularly, to an emitter-follower circuit in which a delay time due to a load capacitance is improved and accordingly an operation speed is increased.
Conventionally, an emitter-coupled type logic circuit, ECL circuit, is known as a digital logic circuit which is capable of operating at a high speed. The ECL circuit has an emitter-follower circuit at an output stage for the purpose of enhancement of the driving capability for the load applied thereto. It has been a general practice to have the emitter-follower circuit formed with an emitter-follower transistor and a terminating resistor, between the ground potential and a first negative power supply potential V.sub.EE (generally, -4.5 V or -5.2 V is adopted). However, the trend in the recent years is that, in order to decrease power consumption of the circuit, such an emitter-follower circuit is often formed between the ground potential and a second negative power supply potential V.sub.T (generally, -2 V). This trend is more remarkable in integrated ECL logic circuits with high packing density.
In the conventional emitter-follower circuit, it has been a drawback that, in the transition of the output signal changing from its High to Low level, the delay time which is determined by the time constant of the value of the load capacitance and the value of the terminating resistor is greatly increased depending on the increase in the capacitance of the load so that the operation speed of the circuit is lowered. If, in such conventional emitter-follower circuit, the resistance value of the terminating resistor is made small in order to decrease the delay time, the current which flows in the terminating resistor increases when the output signal is High so that the level of the High output signal is lowered thereby deteriorating the noise margin.